FinFET basic cells evaluation for regular layouts

摘要

This work evaluates the use of finFET to design a set of basic blocks targeting a regular layout. The main advantage of this approach is a reduction on area and power consumption when using a regular matrix. Moreover, when Independent Gate (IG) finFET is employed in the design of the basic blocks, results are significantly improved in power and delay. Furthermore, when using IG - FinFETs up to 20% area reduction is estimated.