Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology

摘要

This paper presents the design of an OTA-Miller amplifier of the first integrator of a Switched-Capacitor Multi-bit Sigma-Delta Modulator. The first integrator OTA is the most critical block in Sigma-Delta Modulator due to the high bandwidth, high Slew Rate and low noise requirements. The first integrator OTA specifications are obtained from the Sigma-Delta Modulator designing for low power consumption. The gm/ID methodology is used on the OTA design of the first integrator to reduce the power consumption. This methodology is also applied in the other OTAs of the Sigma-Delta Modulator. The Chopper technique is also implemented to reduce the input referred noise of the first integrator. The SDM with the designed OTAs using the gm/ID methodology is simulated by the Spectre simulator. Implemented in 0.18 µm CMOS technology, the SDM achieves a 96 dB SNR for 20 kHz signal bandwidth and a power consumption of 2.77 mW for a 1.8 V supply.