A methodology for optimal design of the reverse-scaled interconnect stack is used to optimize the interconnect crosssectional aspect ratios to increase performance or reduce area. For a 100nm generation macrocell in a GSI System-on-a-Chip (GSoC), using an optimal aspect ratio is demonstrated to achieve 40% increase in clock frequency or 53% decrease in macrocell area. The effects of inductance and repeater insertion on the optimum aspect ratio are illustrated using a case study from the 45nm technology generation. Comparison with a commercial 130nm process generation shows good matching with the model predictions for the aspect ratios of the upper metal levels, while recommendations are suggested for a better design of the lower metal levels.
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