This paper describes a novel technique to derive a pure-spectral system clock from a frequency modulated (FM) signal. The dividing factor is modulation data compensated and ΣΔ dithered. The technique is used for a transmitter based on an all-digital phase-locked loop (PLL) to generate a higher-frequency clock for baseband signal processing, but can also be applied in other transmitters or receivers, especially, if only a slow reference clock is available and a faster system clock is needed. The quality of the generated clock signal depends almost only on the quality of the local oscillator the clock signal is derived from. In the FM-radio transmitter a generated 1.048576 MHz clock signal with 515 ps root mean square (RMS) jitter is generated. The signal can also be used in external circuits.
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