DESIGN-AWARE RIE PROCESS OPTIMIZATION FOR VIA/CONTACT PATTERN TRANSFER

摘要

A novel model-based full-chip algorithm provides a capability to control the design specific variation in pattern transfer caused by via/contact etch processes. This physics based algorithm is capable to detect and report etch hotspots based on the fab defined thresholds of acceptable variations in a prospective dry etch process step. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel via-contact etch (VCE) EDA tool for the design aware process optimization in addition to the "standard" process aware design optimization (DFM).