A low-power, high-speed logic style using Passive Precharge and Rippled Power is proposed. Ultra-low threshold voltage (Vt) devices permit high speed operation, while the heavy leakage current pre-charges dynamic nodes. High Vt devices prevent leakage through the logic. The high Vt devices provide power to evaluate a sequence of logic gates and are activated in series for periods of time which are short relative to the clock period. The power effectively ripples through the logic path. These innovations combine to produce low power circuits that maintain very high speeds. A 16 bit by 16 bit multiplier was simulated in HSPICE using this logic style. We achieved a clock rate of 1 GHz with a latency of 1.3 ns. At that clock frequency the power dissipation is 10.9 mW.
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