The advent of 90nm and 65nm technology nodes caused design teams to face a concurrent "3-on-1" assault of massive designs, significant increase in functional requirements, and substantial process modeling complexities. While existing solutions have done well in carving out their niches by solving just one of these three challenges, they impose significant user intervention and manual iterations for the rest. The current crop of EDA tools were not developed to handle the 50M-gate capacity offered by a 90nm die. The sheer complexity of the design functionality coupled with process variations has proven them inadequate for design closure. Finally, the lack of implicit support for variability routinely produces chips with sub-optimal yield. New approaches to achieve closure for multi-million gate designs, with rapid execution times, and accurate modeling of pervasive process effects are needed for these technology nodes. We will discuss the salient engineering and technological challenges of buildingsuch a system and provide insights into design trade-offs that will help us achieve this seemingly "holy grail" of digital physical design.
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