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Minimization of chip size and power consumption of high-speed VLSI buffers

机译：最小化芯片尺寸和高速VLSI缓冲器的功耗

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《International symposium on Physical design》|1997年|P.186-191|共6页
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D. Zhou; X. Y. Liu;
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中图分类半导体技术;
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专利

1. Power consumption estimation in CMOS VLSI chips [J] . Dake Liu, Svensson C. IEEE Journal of Solid-State Circuits . 1994,第6期

机译：CMOS VLSI芯片中的功耗估算
2. An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi- src="/images/tex/26741.gif" alt="mathrm{V}_{rm DD}"> CMOS/SIMOX Techniques [J] . Shibata Nobutaro, Ohtomo Yusuke, Nishisaka Mika, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第6期

机译：具有2.5 Gb / s / Pin输入/输出缓冲器的STM-16帧终端VLSI：高速和低功耗Multi- src =“ / images / tex / 26741.gif” alt = “ mathrm {V} _ {rm DD}”> CMOS / SIMOX技术
3. On-chip linear voltage regulator module (VRM) effect on power distribution network (PDN) noise and jitter at high-speed output buffer [J] . Kim Heegon, Kim Sukjin, Kim Joungho, Electromagnetic Compatibility Magazine, IEEE . 2015,第2期

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4. Criteria to minimize power consumption of frequency domain equalizers in VLSI implementations [C] . Elvio Serrano, Pablo Quiroga, Alfredo Taddei, Workshop on Information Processing and Control . 2015

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5. Application of Random Walks for the Analysis of Power Grids in Modern VLSI Chips. [D] . Boghrati, Baktash. 2013

机译：随机游走在现代VLSI芯片电网分析中的应用。
6. A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification [O] . Wei He, Jinguo Huang, Tengxiao Wang, 2020

机译：一种高速低成本VLSI系统能够用于动态视觉传感器数据分类的片上在线学习
7. Analysis of High-Speed Modes of Steel Cold Rolling to Minimize Power Consumption in Workshop no.11 at OJSC «Magnitogorsk Iron and Steel Works» [O] . Evgeny Ishmetyev, Dmitrij Chistyakov, Alexander Panov, 2016

机译：钢冷轧钢高速模式清除OJSC«Magnitogorsk钢铁工程车间工程中的功耗最大限度地

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