Overflow handling in inner-product processors

摘要

Several DSP applications demand high speed inner-product processors (IPP). Most current implementations of IPP use the multiply-accumulate (MAC) concept to perform the IP operations. Rather than using MAC accumulate to perform the IP operation, the authors show two superior designs, MIPP and CSIPP, that outperform the standard implementations. The speed improvement ratio is estimated to be between 2 to 4 for both designs. The paper also presents a new technique to detect and correct overflow occurrence in MIPP and CSIPP.