Fast VLSI architectures using non-redundant multibit recoding for computing exponentiation modulo a positive integer

摘要

Architectures for fast evaluation of A/sup 2/ mod N have been developed. These are based on the application of the Primlani-Meador technique, recently proposed for nonredundant radix-4 multiplication, together with the technique of E. Lu et al. (1988) for A/sup 2/mod N evaluation. Complete design details with extensions to multibit recoding considering an even number of bits at a time while requiring the evaluation of fewer partial products are presented.