A new arbitration circuit for asynchronous multiple bus multiprocessor systems

摘要

In a bus-based multiprocessor system, a bus arbitration circuit is necessary to assign the bus(es) to the requesting devices. The authors first discuss some design flaws of an existing asynchronous arbiter for multiple bus systems, and then present another design for an asynchronous arbiter which is simple, inexpensive and easy to implement. This circuit has been built and tested. The performance of this new arbiter was also measured by developing a software simulation model. The performance was measured in terms of fairness and mean-arbitration-time. The performance results are given.