ULTRA-SHALLOW JUNCTION FORMATION USING ION IMPLANTATION AND RAPID THERMAL ANNEALING: PHYSICAL AND PRACTICAL LIMITS

摘要

Both n- and p-type drain extensions that meet the ITRS requirements for the 100-nm gate-length technology node can now be formed using optimized implantation and annealing processes. The optimization consists of reducing the dopant ion-implantation energy to the sub-keV range (for boron) and of reducing the thermal budget by spike annealing ("zero" dwell time at temperature). Here we review the impact of physical phenomena such as dopant self-sputtering and transient enhanced diffusion during the spike anneal which practically limit the formation of shallower or less resistive junctions by implantation and rapid thermal annealing.