An Analytical Model for Instruction Fetch Performance of a Trace Cache Microarchitecture

摘要

Wide-issue super-scalar processors can execute several program blocks in a cycle. Regular instruction cache fetch mechanisms are not capable of supporting this high fetch bandwidth requirement. Several improvements of the fetch mechanism are currently in use. One of the most successful of these improvements is the addition of an instruction memory structure known as Trace Cache. In this paper an analytical model for instruction fetch performance of a trace cache microarchitecture is presented. Parameters, which affect trace cache instruction fetch performance, are explored and several analytical expressions are presented. The presented model can be used to understand performance tradeoffs in trace cache microarchitecture design. Results from the validation of the model are presented. The model is implemented in a computer program named Tulip. Results from Tulip, which show how different parameters affect performance, are also presented.