Estimation of On-Chip Simultaneous Switching Noise in VDSM CMOS Circuits

摘要

On-chip simultaneous switching noise (SSN) has become an important issue in the design of power distribution networks in current VLSI/ULSI circuits. An analytical expression characterizing the simultaneous switching noise voltage is presented here based on a lumped RLC model. The waveform describing the SSN voltage is quite close to the waveform obtained from SPICE. The peak value of the simultaneous switching noise voltage based on this analytical expression is within 10% as compared to SPICE simulations.