Mobility Degradation and Current Loss due to Vertical Electric Field in Channel Area of Submicron MOS Devices

摘要

In this work we show quantified modeling results for the effect of gate-voltage-induced mobility degradation on MOS device current. Presented results are for three technologies, i.e. 0.50μm, 0.35μm, and 0.25μm, and are based on extractions from measured data. Quantified results show that the calculated current loss due to this type of mobility degradation is increased with technology scaling and is reduced at higher temperatures. Measured values of the access resistance of the MOS devices for the three technologies as a function of temperature are also presented.