High Performance Single Chip Implementation for a Digital Protective Relay Using FPGA

摘要

Lack of extra parallelism in the existing microprocessor/DSP-based protective relay, can be overcome by designing it as the specialized hardware. In this paper, we present the new efficient field p rogrammable gate a rray (FPGA) implementation for a digital protective relay, which is primarily composed of a data processing block, several measurement units and a multifunctional protection algorithm block. A single discrete Fourier transform (DFT) filter, used in removing DC offset and harmonics for obtaining fundamental frequency component, is effectively implemented by sharing all possible operators. The protection algorithm block provides a group of highly accurate processes for supporting both instantaneous and inverse time characteristics with minimized quantization error. This design can be an advanced alternative to the conventional microprocessor/DSP-based protective relaying system in terms of speed, area efficiency and protection behavior.