HiDRA: A New Architecture for Heterogeneous Embedded Systems

摘要

This paper proposes an architecture for heterogeneous embedded systems based on multiple reactive processor cores. The architecture supports globally asynchronous locally synchronous systems with a mix of data flow and control flow behaviors. The reactive processor cores implement Esterel-like computation, and also have primitives for basic concurrency, which can further be used to implement more advanced communication mechanisms. Unlike known languages and models of heterogeneous embedded systems that work at the simulation level, the proposed architecture serves as a direct executable platform and may be used for rapid prototyping. Performance comparison with systems realized from system-level language ECL reveals significant speedup and reduction in code size.