FPGA implementation of a novel architecture for PCR related measurements in DVB-T

摘要

In the DVB domain, the MPEG-2 transport stream carries, in addition to audio and video data, a Program Clock Reference (PCR). The PCR is used to synchronize the MPEG-2 decoder clock in multimedia receiver. The PCR values can be affected by an offset inaccuracy due to encoder imperfection or can be affected in arrival time by jitter. The measurement of different PCR parameters like drift, precision and jitter are necessary for evaluating the decodability efficiency. These measurements are generally achieved using a Phase Lock Loop (PLL) and a set of measurements filters as it is recommended in the standard for the measurement of the Quality of Services (QoS) in DVB-T. In this paper, we propose a real-time measurement system for the analysis of PCR related parameters. The ADPLL and the associated set of measurement filters are implemented in an FPGA and the experimental results are presented.