Abstract: In implementation of hybrid compression algorithms, the Huffman or Modified Huffman codec can consume a significant portion of silicon real-estate or CPU cycles. To reduce this cost, several schemes have been published that take advantage of one or more inherent properties of the variable length code tables. This paper examines some of these properties and their corresponding architectural components which can be pieced together to form custom hybrids suited to specific applications. Hardware architectural classifications include: serial and parallel Trees, Content Addressable Memory, Programmable Logic Arrays, and parallel comparators schemes that resemble flash A/D architectures. Assessment criteria include: bit rate vs. symbolic rate performance, clock cycle ratios, latencies, pre-buffering and post- buffering, codebook and source channel statistical dependencies, encoder and decoder circuitry sharing, pre-processing of codebooks, critical path, register use in software, breakdown between memory and logical operators, custom vs. standard cells, and code word order. Finally, the performance and size of current industrial implementations for specific application (JPEG, MPEG) are summarized.!9
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