Fabrication and Dielectric Breakdown of 3C-SiC/SiO

摘要

O annealed devices using the high-low method. Gate oxide was biased with elevated voltage and the distribution of cumulative failed devices was studied. Two failure mechanisms were identified with mechanism 1 dominating the 6-8.5MV/cm range, and mechanism 2 becoming more obvious above S.5MV/cm. The failure rate of fabricated MOS capacitors with a diameter of 100μm at 3MV/cm and room temperature was estimated to be ~3450 PPM.