Realization of vertical P~+ wall through-wafer

摘要

P~+ walls through wafer can be considered as key regions in the 3D architecture of new bi-directional current and voltage power integrated devices. Moreover, these P~+ walls can be used as electrical vias in the design of microsystems, in order to make easier 3D packaging. In this paper, we demonstrate the possibility of fabricating these P~+ walls combining the deep RIE of silicon and deposit of boron-doped polysilicon.