PERFORMING THE SOFT-ERROR RATE (SER) ON A TDBI CHAMBER

摘要

As the gate oxide gets thinner and the cell density is increased due to continuous scaling and the rapid technology advancement, the soft-error rate (SER) attracts many researchers' attentions. In the IC industries, engineers perform the accelerated (ASER) and the system soft-error rate (SSER) tests to evaluate SER performance. ASER and SSER tests are performed on memory testers and they are time and cost consuming especially for SSER, which is a test with large sample size and long test time. In this paper, we successfully use a Test During Burn-In (TDBI) chamber for SER tests with good correlation with the memory tester to contribute a cost reduction solution. We also successfully verify the relationships of either the technology or Vcc and the Failure-In-Time (FIT) level by real cases. Also, we report some significant findings like the Burn-In (BI) effect and the test pattern issue for different circuit designs.