With the proliferation of transistor count in VLSI design, more and more desing groups try to figure out a way to efficiently combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical floorplan desing can be adequately solved in the Internet environment. In this paper, we address the problem of area minimization floorplan desing in the Internet environment. We propose a novel algorithm, RMG algorithm. Taking advantage of the Internet, RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. With creating floorplan design in the Internet environment, it can be seen that the Internet advantages Electronic Design Automation (EDA).
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