The Hierarchical h-Adaptive 3-D Boundary Element computation of VLSI Itnerconnect Capacitance

摘要

In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The Boundary Element Method(BEM) is an effective tool for solving Laplacian's equation applied in the parasitic capacitance extraction. In this paper, a hierarchical h-adaptive BEM is presented. It constructs a 3-D linear hierarchical shape function based on constant boundary element and uses previous computations and solutions. Hence, it reduces much computations and solutions. Hence, it reduces much computation in adaptive procedure. Besides, a combination of residual-type estimator and reduced Z-Z error estimator for more reliable and efficient estimation of error is presented. Some numerical results show that this method is effective.