Research and Implementation of Parallel Algorithm for CRC-32 Calculation

摘要

According to IEEE 802.3z, CRC-32 is applied to MAC layer of the Gigabit Ethernet. The speed of transmitting data in the Gigabit Ethernet reaches to 1.25Gbits/s, so the serial realization of CRC-32 in the Gigabit Ethernet is very difficult. After having analyzed the principle of CRC calculation, this paper presents a high-efficient parallel algorithm for the CRC-32 calculation with 8-bit parallel data input based on studying of serial realization. Compared with the traditional parallel algorithm based on state transition matrix, the new algorithm uses a simpler state transition equation, thus easier to implementation. Additionally, it needs fewer memorizers than the table lookup algorithm but has better performance. The module for the CRC-32 calculation with any bytes parallel data input has been realized in certain FPGA chip, only 93 logic cells are used, but data throughput can be 270M×8bits/s.