首页> 外文会议>7th annual international wafer-level packaging conference amp; tabletop exhibition 2010 >SCALABLE INTERCONNECT TECHNOLOGY THAT ENABLES HIGH DENSITY, HIGH PERFORMANCE AND LOW PROFILE CONNECTIVITY FOR BOARD TO BOARD, PACKAGE TO BOARD AND BOARD TO FLEX APPLICATIONS
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SCALABLE INTERCONNECT TECHNOLOGY THAT ENABLES HIGH DENSITY, HIGH PERFORMANCE AND LOW PROFILE CONNECTIVITY FOR BOARD TO BOARD, PACKAGE TO BOARD AND BOARD TO FLEX APPLICATIONS

机译:可扩展的互连技术,可实现板对板,板对板和板对柔性应用的高密度,高性能和低轮廓连接性

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As chip scale packages migrate to finer pitch, high density interconnect substrate technology co-evolves to provide the higher interconnect needs. But the load board, with its large area, thick substrate and many layers cannot keep up. While integrating a few high density interconnect layers on top of a conventional load board to do the geometry transformation is being done, it is very expensive in direct cost and in yielded cost. An alternative solution is to adopt the approach for testing a single die or whole wafer: add a space transformer from the fine pitch pads of the device to the coarse pitch pads of the circuit board. After all, needle probe cards have been doing this for many years. Other technologies have evolved for wafer probing that use a ceramic substrate as the space transformer. In many probe cards, for example, MEMs compliant tips are fabricated on the top of the ceramic substrate on pitches as fine as 2 mils [4]. The pads on the bottom of the ceramic substrate interface to the load board with another compliant one to one interposer but on pitches of 50 to 100 mils [4]. This same approach can be implemented for final test of packaged devices. A daughter board acts as the space transformer from the finer pads pitch of the CSP to the coarser pad pitch of the load board. A fine pitch socket technology is used on the top surface and a board to board interposer is used between the daughter card and the conventional load board. Highlighted in this article is such a board-to-board interposer from HCD Inc. High Connection Density's interconnect technology enables high speed, high current & low profile connectivity reducing the cost of test for board to board, package to board and flex to board connections and in today's world of increasing pin count and high performance applications, it is the technology of choice with excellent electrical performance and reliable contact.
机译:随着芯片级封装向更细间距的迁移,高密度互连基板技术不断发展以提供更高的互连需求。但是具有大面积,厚基板和多层的负载板无法跟上。在完成将一些高密度互连层集成到常规负载板顶部以进行几何变换的同时,直接成本和成品成本非常昂贵。另一种解决方案是采用测试单个裸片或整个晶圆的方法:从设备的细间距焊盘到电路板的粗间距焊盘之间添加一个空间变换器。毕竟,针探针卡已经做了很多年了。已经开发出其他技术来进行晶片探测,这些技术使用陶瓷衬底作为空间变换器。例如,在许多探针卡中,兼容MEM的针尖都以2密耳的精细间距制造在陶瓷基板的顶部[4]。陶瓷基板底部的焊盘通过另一种兼容的一对一中介层与负载板连接,但间距为50到100密耳[4]。可以对封装的设备进行最终测试时采用相同的方法。子板充当从CSP的较细焊盘间距到负载板的较粗焊盘间距的空间变换器。顶面采用了细间距插座技术,子卡和常规负载板之间使用了板对板中介层。本文重点介绍的是HCD Inc.的板对板中介层。高连接密度的互连技术可实现高速,高电流和薄型连接,从而降低了板对板,封装对板以及柔性对板连接的测试成本在当今不断增加的引脚数和高性能应用的世界中,它是具有出色电气性能和可靠触点的首选技术。

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