Investigation of performance improvement and gate-to-junction leakage reduction for the 90nm CMOS gate stack architeture

摘要

An Investigation of the gate stack for 90nm gate Length CMOS is presented. The optimised 90nm nMOS and pMOS transistors exhibit state of the an DC and switching characteristics. Nominal nMOS and pMOS drive currents of 760μA /μm and 320 μA /μm with an Ioff state current of 2nA /μm (V_(DD) =1.2V) have been realized. An inverter delay of 15ps at 1.2V operating voltage has also been measured.