GATE MODEL EXTRACTION FROM CMOS TRANSISTOR CIRCUITS

摘要

All VLSI designs are ultimately implemented at the transistor level. Transistor Mapped Binary Decision Diagram (TM-BDD) is a special class of BDDs representing inverting Boolean functions. There is a one-to-one correspondence between a CMOS transistor circuit and its TM-BDD. This paper presents a novel approach to perform the functional and timing model extraction from a CMOS transistor circuit. Gate model can be automatically extracted from its TM-BDD which is one-to-one corresponding to a transistor circuit. The static pinto-pin first-order RC timing model, associated with each extracted gate to directly reflect the number of transistors conducting in series, can be also extracted from its TM-BDD. The accurate timing model can be characterized by SPICE simulations with piecewise linear waveforms which can be automatically constructed from input stimuli generated from TM-BDD, pre-defined input slews and output loads. The integration of functional and timing models allows full utilization of design synthesis, design for testability and static timing analysis.