A 12-bit 3 MS/s asynchronous comparator-based cyclic ADC with an adjustable threshold voltage comparator

摘要

In this paper, we propose an asynchronous comparator-based cyclic analog-to-digital converter (ADC) with an adjustable threshold voltage to improve the conversion rate that is limited by the long charging and discharging time in the conventional comparator-based switched capacitor (CBSC) circuit. Our asynchronous timing and the adjustable threshold voltage of the comparator improves the conversion rate by reducing undesired undershoot and overshoot of the residual signal, keeping the advantages of the CBSC circuit such as low supply voltage operation and low power consumption. Post-layout simulation results show that the signal-to-noise and distortion ratio (SNDR) is 64.9 dB and a spurious-free dynamic range (SFDR) is 69.7 dB at the sampling rate of 3 MS/s and the Nyquist rate input frequency. The chip is designed with a 0.18 μm CMOS process and has an effective area of 0.25 mmn²nand a power consumption of 1.6 mW at 1.8Vsupply.