The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
Air and Missile Defense College, Air Force Engineering University, xi'an 710051, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
The Institute of Microelectronics, Tsinghua University, Beijing 100084, China;
Clocks; Receivers; Jitter; Voltage-controlled oscillators; IP networks; CMOS technology; Optical signal processing;
机译:具有低开销技术的56 Gb / s PAM4接收器,用于在65 nm CMOS中对阈值和基于边缘的DFE FIR和IIR-Tap进行自适应
机译:具有双击直接判定反馈均衡的60 Gb / s PAM4有线接收器,采用28-NM CMOS中的轨道和再生切片机
机译:采用65 nm CMOS技术的60 Gb / s 173 mW有线接收器前端的设计技术
机译:65-NM CMOS技术的80-GB / S PAM4有线接收器设计
机译:CMOS技术中用于光学互连的高速发送器和接收器的设计和实现。
机译:用于空间光通信的CMOS光脉冲接收器单元阵列的设计与实现
机译:具有双击直接判定反馈均衡的60 Gb / s PAM4有线接收器,采用28-NM CMOS中的轨道和再生切片机