首页> 外文会议>2016 IEEE 37th International Electronics Manufacturing Technology amp; 18th Electronics Materials and Packaging Conference >Steps to prevent quality and reliability issues resulted from design optimization for productivity improvement
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Steps to prevent quality and reliability issues resulted from design optimization for productivity improvement

机译:为提高生产率而进行的设计优化导致了防止质量和可靠性问题的步骤

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Productivity improvement in manufacturing is always the key focus to strengthen an enterprise cost position to stay ahead of competition. In semiconductor manufacturing, improve the cost position through faster machine speed, reduce man to machine ratio, utilization of material efficiently, increase the through put per fix process cycle, and etc. are the common practices. In this paper, cost improvement is achieved through maximizing the number of packages per fix dimension of leadFrame (LF) and with minimum investment. The unit density per area of the LF has increased by 60% mainly through the introduction of through-gate design and increased number of rows per LF by 30%. However, the introduction of these measures have also increased the complexity of all the processes to manufacture the SSO8 package. The main focus of this study is on molding process. Upfront steps are taken to optimize the design so that unwanted quality and reliability issues during qualification and ramp-up phase can be eliminated. With the through gate design the compound flow mechanics and rheology that can create wire sweep, incomplete fill, and compound wettability are thoroughly examines and analyzed before the design is frozen. The upfront analysis on the technical challenges and numerical models are used to predict the interactions between material behavior and the tool designs. The results at qualification and ramp-up showed that molding related issues can be greatly minimized and project timeline can be met. Investment is minimized by designing the frame dimension to the existing machine maximum capacity except trim and form machine.
机译:制造业生产力的提高始终是加强企业成本地位以保持竞争优势的关键重点。在半导体制造中,通常的做法是通过更快的机器速度来改善成本状况,降低人与机器的比率,有效地利用材料,增加每个固定处理周期的产量等。在本文中,通过最大化LeadFrame(LF)的每个固定尺寸的封装数量并以最小的投资来实现成本改善。 LF单位面积的单位密度增加了60%,这主要是由于引入了直通门设计,每个LF的行数增加了30%。但是,这些措施的引入也增加了制造SSO8封装的所有过程的复杂性。这项研究的主要重点是成型工艺。采取了前期步骤来优化设计,从而消除了在资格鉴定和升级阶段中不必要的质量和可靠性问题。通过直通门设计,在冻结设计之前,会彻底检查和分析可能造成焊丝刮擦,填充不完全和化合物润湿性的化合物流动力学和流变性。对技术挑战和数值模型的前期分析用于预测材料性能和工具设计之间的相互作用。鉴定和试产的结果表明,与成型相关的问题可以大大减少,并且可以满足项目时间表。通过将框架尺寸设计为除修剪和成型机之外的现有机器最大容量,可以最大程度地减少投资。

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