An adaptive virtual overlay for fast trigger insertion for FPGA debug

摘要

Field-programmable gate-array (FPGA) platforms are commonly used for prototyping complex designs, allowing designers to evaluate and validate the functionality at speeds that are orders of magnitude faster than simulation. To counter the limited observability of hardware, on-chip trace buffers are used to record the behaviour of a small subset of signals. To effectively use the limited capacity of these on-chip trace buffers, trigger circuitry is required to determine when to start and/or stop recording signal behaviour. Although it is possible to implement the trigger circuitry and add it to the user circuit at compile time, this would require recompiling a design every time the trigger circuit is modified, reducing debug productivity. In this paper, we present and evaluate an adaptive virtual overlay architecture for rapid trigger implementation. The overlay is built from logic and routing resources not used by the user circuit, reducing the overhead and impact on the user circuit. At debug time, the pre-synthesised overlay architecture can quickly be configured to implement the desired trigger functionality. We show that our overlay architecture provides flexibility required for mapping trigger circuitry with negligible impact on delay. We also show trigger mapping is significantly faster rather than recompile insertion, increasing debug productivity.