An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine

摘要

Many applications use encryption to protect data confidentiality, which require decryption before any data processing. Integrating ASIC design of encryption engines and general-purpose processor can yield the best overall performance in program execution as it benefits from low latency hardware engine and high processor memory bandwidth. However, ASIC design is fixed once manufactured, which cannot afford any changes in the implemented cryptographic algorithm. FPGA implementation is attractive in terms of its re-configurability but it is generally much slower than ASIC design. In this demo, we present a novel scheme that can offload the latency of reconfigurable cryptographic engine from the overall execution and define an en-/decryption data interface, which is independent of the underlying encryption algorithms. To verify our proposed scheme, we implemented a FPGA prototype, which integrated our design with OpenRISC on ALTERA DE2i-150 evaluation board. We prove that our proposed architecture can flexibly and efficiently en-/decrypt the data with zero overheads towards overall program execution with careful design. Our case study on SQLite shows that the query execution over a 1GB encrypted database on our implemented system introduces performance overhead ranging from 0% to 14%.