Implementation of an ALU using modified carry select adder for low power and area-efficient applications

摘要

In digital computer, an Arithmetic logic unit (ALU) is a powerful combinational circuit that executes arithmetic and logical functions. Parallel adder in ALU plays an essential role, however the carry propagation (CP) takes most of the time for addition. For Low power and area-efficient applications, ALU using modified Square Root Carry Select Adder (SQRT CSLA) is proposed and for better speed applications, ALU using modified SQRT CSLA by Carry Look Ahead (CLA) Adder is implemented. The paper delivers the design and implementation of 8-Bit, 16-Bit, 32-Bit and 64-Bit ALU using modified SQRT CSLA and also compares it with the ALU using regular SQRT CSLA in terms of total number of basic gates. The design entry is done in Verilog Hardware Description Language (HDL) and simulated using ISIM Simulator. It is synthesized and implemented using Xilinx ISE 12.2. By using ALU with modified SQRT CSLA, 20.44% reduction in basic gates is observed.