Dept. of Electron. Commun. Eng., Tampere Univ. of Technol., Tampere, Finland;
circuit optimisation; field programmable gate arrays; logic design; IEEE-802.11n demodulator; Stratix-V field programmable gate array; clock speed control; coarse grain reconfigurable array; constraint driven frequency scaling; fast Fourier transform processing; feedback control system; power dissipation; power efficiency; self-optimizing coprocessor model; self-optimizing processor model; Avatars; Clocks; Feedback control; Phase locked loops; Power dissipation; Reduced instruction set computing;
机译:粗粒度可重配置处理器阵列中的可扩展多域电源门控
机译:粗粒度间可重配置体系结构重配置技术,可在基于粗粒度可重配置体系结构的多核体系结构上有效地流化内核流
机译:粗粒度可重新配置的基于阵列的加速器的自动调整CNN
机译:粗粒可重构阵列中的约束驱动频率缩放
机译:粗晶可重新配置阵列的偏移管线
机译:使用单层和双层减层石墨烯碳带阵列的频率可重构广角太赫兹吸收器
机译:基于软粗粒度可重构阵列的高级综合方法:提高设计效率并探索极高的FpGa频率