16-bit velocious fault lenient parallel prefix adder

摘要

Fault tolerance has an important role in modern digital systems were immediate human intervention is not possible and system failure can have disastrous consequences. Parallel Prefix Adder has been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs. As Kogge-Stone has inherent redundancy in the carry tree, a fault tolerant parallel prefix adder can be implemented using it. Kogge-Stone design can only perform fault correction, but no detectability, so it is good to use Sparse Kogge-Stone to achieve this. Existing method utilizes a Sparse Kogge-Stone adder that is capable of both fault detectability and fault correction. Sparse Kogge-Stone adder is a combination of carry tree chains and Ripple Carry Adders. This paper proposes a high speed fault tolerant parallel prefix adder. Here, the Ripple Carry Adders in the Sparse Kogge-Stone address is replaced by Carry Select Adders to achieve high speed of operation. Two additional Carry Select adders allows fault tolerance to be achieved. Synthesis and simulation for an FPGA platform are carried out. For very large bit widths, there are indications that the sparse Kogge-stone adder offers superior performance over a Ripple Carry Adder when implemented on an FPGA.