Sampled-data controller implementation

摘要

The setting of this paper is the implementation of timed discrete-event systems (TDES) as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs. In this paper, we establish a formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller as well as a set of modular controllers, and show that they will produce equivalent output. We also discuss a flexible manufacturing system (FMS) example and present some FSM translation issues encountered, as well as the FSM version of some of the system's supervisors.