首页> 外文会议>2012 10th IEEE International Conference on Semiconductor Electronics. >Design of single-stage folded-cascode gain boost amplifier for 14bit 12.5Ms/S pipelined analog-to digital converter
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Design of single-stage folded-cascode gain boost amplifier for 14bit 12.5Ms/S pipelined analog-to digital converter

机译:用于14位12.5Ms / S流水线模数转换器的单级折叠共源共栅增益升压放大器的设计

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This paper describes the design and simulation of a fully-differential, high gain, high speed CMOS Operational Transconductance Amplifier (OTA). The op-amp is designed for unity gain sampler stage of 14bit 12.5Ms/s pipeline analog-to digital converter. The design is implemented using a folding cascode topology with the addition of gain boosting amplifiers for increased gain. Common-mode feedback (CMFB) is used to stable the designed OTA against temperature and other process variations. This design has been implemented in 0.13μm IBM RF mixed signal CMOS Technology. The Spectre simulation shows the DC gain of 91.5 dB and a unity-gain frequency of 714.5MHz with phase margin of 62° (double 7.5-pF load) while consuming 9 mW power. For the normal corner, the settling time to 1/2 LSB of 14bit A/D converter accuracy is 40 ns.
机译:本文介绍了一种全差分,高增益,高速CMOS运算跨导放大器(OTA)的设计和仿真。该运算放大器专为14位12.5Ms / s流水线模数转换器的单位增益采样器级设计。该设计使用折叠共源共栅拓扑结构实现,并增加了增益提升放大器以增加增益。共模反馈(CMFB)用于稳定设计的OTA免受温度和其他过程变化的影响。该设计已在0.13μm的IBM RF混合信号CMOS技术中实现。 Spectre仿真显示DC增益为91.5 dB,单位增益频率为714.5MHz,相位裕量为62°(双倍7.5pF负载),而功耗为9 mW。对于正常拐角,14位A / D转换器精度达到1/2 LSB的建立时间为40 ns。

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