Design of a 9-bit UART module based on Verilog HDL

摘要

Universal Asynchronous Receiver Transmitter (UART) is widely used in data communication process especially for its advantages of high reliability, long distance and low cost. In this paper, we present the design of 9-bit UART modules based on Verilog HDL. This design features automatic address identification in the character itself. We have implemented the VLSI design of the module and pass data between the proposed 9-bit UART module with a host CPU. The design consists of receiver module, transmitter module, prescaler module and asynchronous FIFOs. We have explained the functions of each individual sub-modules and how the design works in simulation.