Low computational complexity hardware implementation of Laplacian Pyramid

摘要

In this paper a new implementation of the Laplacian Pyramid (LP) algorithm is proposed which uses the polyphase representation and noble identities to facilitate a new pipeline architecture. Our approach saves a large number of mathematical operations which results in the reduction of power consumption. Furthermore, the proposed architecture decreases the number of employed resources as compared with the existing designs. The implementation results reveal the correct functionality of the proposed architecture.