High-Voltage LDMOS Compact Modelling

摘要

In compact modelling of high-voltage LDMOS devices often a sub-circuit approach is used. While for the channel region a standard compact MOS model (for example BSIM4, MM11 or PSP) is used, the drift region is described by a compact JFET model. We will show that using this conventional approach the effects of the widening of the depletion region in the lateral direction cannot be taken into account properly. As a consequence the voltage at the internal node between channel and drift region becomes unphysical and accurate physics-based capacitance modelling becomes unfeasible.rnIn this paper we will introduce a new approach for compact LDMOS modelling to remedy these shortcomings. Next this new approach is compared with device simulations and measurements for both currents and capacitances. Finally we describe the method to implement this approach in a circuit simulator.