Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation

摘要

Various methods for calculating regional charge storage components in bipolar transistors from device simulation results are compared with respect to their suitability for compact modeling. The methods are evaluated for Si and SiGe transistors with very different doping profiles representing existing process technologies. Causes for the failure of a certain method under certain conditions are discussed. Such regional partitioning methods are also very useful for process development.